Dominik Walter - Lehrstuhl für Informatik 12

Dominik Walter

Department Informatik (INF)
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
dominik.l.walter@fau.de

Cauerstr. 11
91058 Erlangen
Raum 02.131

Curriculum Vitæ

since 2019	Researcher at the Department of Computer Science 12 (Hardware-Software-Co-Design), University of Erlangen-Nuremberg, Germany
2016 − 2019	M.Sc. Computer Science University of Augsburg, Germany
2013 − 2016	B.Sc. Computer Science and Multimedia University of Augsburg, Germany

Research Projects

Invasive Computing

Publications

2025

Spieck J., Walter D., Waschkeit J., Teich J.:
Co-Design of Sustainable Embedded Systems-on-Chip
Design, Automation and Test in Europe Conference 2025 (Lyon, 31. März 2025 - 2. April 2025)
In: Design, Automation and Test in Europe Conference 2025
BibTeX: Download
Spieck J., Walter D., Waschkeit J., Teich J.:
Co-Design of Systems-on-Chip for Sustainability
NG-RES 2025: Sixth Workshop on Next Generation Real-Time Embedded Systems (Barcelona, Spain, 20. Januar 2025 - 22. Januar 2025)
DOI: 10.4230/OASIcs.NG-RES.2025.3
URL: https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2025.3
BibTeX: Download
Walter D., Halm M., Seidel D., Ghosh I., Heidorn C., Hannig F., Teich J.:
Evaluation of CGRA Toolchains
1st Workshop on Open Source Solutions for Massively Parallel Integrated Circuits (OSSMPIC) (Lyon, 31. März 2025 - 2. April 2025)
In: In Proceedings of the 1st Workshop on Open Source Solutions for Massively Parallel Integrated Circuits (OSSMPIC) 2025
DOI: 10.48550/arXiv.2502.19114
BibTeX: Download
Walter D., Halm M., Seidel D., Ghosh I., Heidorn C., Hannig F., Teich J.:
Mapping and Execution of Nested Loops on Processor Arrays: CGRAs vs. TCPAs
(2025)
DOI: 10.48550/arXiv.2502.12062
BibTeX: Download

2024

Walter D., Adamtschuk T., Hannig F., Teich J.:
Analysis and Optimization of Block LU Decomposition for Execution on Tightly Coupled Processor Arrays
35th IEEE International Conference on Application-specific Systems, Architectures and Processors (Hong Kong, 24. Juli 2024 - 26. Juli 2024)
In: Proceedings of the IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2024
DOI: 10.1109/ASAP61560.2024.00029
URL: https://ieeexplore.ieee.org/document/10631126
BibTeX: Download
Walter D., Brand M., Heidorn C., Witterauf M., Hannig F., Teich J.:
ALPACA: An Accelerator Chip for Nested Loop Programs
IEEE International Symposium on Circuits and Systems (ISCAS) (Singapore, 19. Mai 2024 - 22. Mai 2024)
In: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2024
DOI: 10.1109/ISCAS58744.2024.10558549
URL: https://ieeexplore.ieee.org/document/10558549
BibTeX: Download

2022

Anantharajaiah N., Asfour T., Bader M., Bauer L., Becker J., Bischof S., Brand M., Bungartz HJ., Eichler C., Esper K., Falk J., Fasfous N., Freiling F., Fried A., Gerndt M., Glaß M., Gonzalez J., Hannig F., Heidorn C., Henkel J., Herkersdorf A., Herzog B., John J., Hönig T., Hundhausen F., Khdr H., Langer T., Lenke O., Lesniak F., Lindermayr A., Listl A., Maier S., Megow N., Mettler M., Müller-Gritschneder D., Nassar H., Paus F., Pöppl A., Pourmohseni B., Rabenstein J., Raffeck P., Rapp M., Rivas SN., Sagi M., Schirrmacher F., Schlichtmann U., Schmaus F., Schröder-Preikschat W., Schwarzer T., Sikal MB., Simon B., Snelting G., Spieck J., Srivatsa A., Stechele W., Teich J., Comprés Ureña IA., Verbauwhede I., Walter D., Wild T., Wildermann S., Wille M., Witterauf M., Zhang L.:
Invasive Computing
FAU University Press, 2022
ISBN: 978-3-96147-571-1
DOI: 10.25593/978-3-96147-571-1
BibTeX: Download
Teich J., Brand M., Hannig F., Heidorn C., Walter D., Witterauf M.:
Invasive Tightly-Coupled Processor Arrays
In: Jürgen Teich, Jörg Henkel, Andreas Herkersdorf (Hrsg.): Invasive Computing, FAU University Press, 2022, S. 177-202
ISBN: 978-3-96147-571-1
DOI: 10.25593/978-3-96147-571-1
BibTeX: Download

2021

Heidorn C., Walter D., Candir YE., Hannig F., Teich J.:
Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays
31st International Conference on Field Programmable Logic and Applications (FPL) (Virtual Conference, 30. August 2021 - 3. September 2021)
In: Proceedings of the 31st International Conference on Field Programmable Logic and Applications (FPL) 2021
DOI: 10.1109/FPL53798.2021.00079
BibTeX: Download
Walter D., Teich J.:
LION: Real-Time I/O Transfer Control for Massively Parallel Processor Arrays
19th ACM-IEEE International Conference on Formal Methods and Models for System Design (Beijing, China, 20. November 2021 - 22. November 2021)
In: Proceedings of the 19th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) 2021
DOI: 10.1145/3487212.3487349
BibTeX: Download
Witterauf M., Walter D., Hannig F., Teich J.:
Symbolic Loop Compilation for Tightly Coupled Processor Arrays
In: ACM Transactions on Embedded Computing Systems (2021)
ISSN: 1539-9087
DOI: 10.1145/3466897
BibTeX: Download

2020

Walter D., Witterauf M., Teich J.:
Real-time Scheduling of I/O Transfers for Massively Parallel Processor Arrays
18th ACM-IEEE International Conference on Formal Methods and Models for System Design, MEMOCODE 2020 (Jaipur, India, 2. Dezember 2020 - 4. Dezember 2020)
In: Proceedings of the 18th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) 2020
DOI: 10.1109/MEMOCODE51338.2020.9315179
BibTeX: Download