Tobias Hahn
Tobias Hahn, M. Sc.
Department Informatik (INF)
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Cauerstr. 11
91058 Erlangen
- Telefon: +49 9131 85-67343
- Faxnummer: +49 9131 85-25149
- E-Mail: tobias.hahn@fau.de
- Webseite: https://www.cs12.tf.fau.de/person/tobias-hahn
Curriculum Vitæ
| Since 3/2021 | Researcher at the Department of Computer Science 12 (Hardware/Software Co-Design) |
| 10/2018 − 2/2021 | Master of Science in Information- and Communication Technology at Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany |
| 09/2015 − 09/2018 | Bachelor of Engineering in Electrical Engineering at DHBW Mosbach, Germany |
Research Projects
Research Interests
- FPGA Accelerators for data stream processing
- Accelerated parsing of semi-structured data formats
- Near-data processing
- Reconfigurable Computing
Teaching
| Summer semester 2024 | |
| Winter semester 2023/2024 | |
| Summer semester 2023 | |
| Winter semester 2022/2023 | |
| Summer semester 2022 | |
| Winter semester 2021/2022 | |
| Summer semester 2021 |
Supervised Theses
- Optimistic Parsing of JSON Data on FPGAs (MT)
- Dictionary-based Compression and Decompression of JSON-encoded data on FPGA-based SoCs (BT)
- Automatic generation of optimistic stream processing FPGA accelerators leveraging probabilistic data structures (MT)
- Entwurf eines Avro-Befehlssatz-Parsers für FPGAs (MP)
- FPGA-basierte Avro-Parser für beschleunigte Datenstromverarbeitung (BT)
- Acceleration of 3D Stencil Applications Using High-Bandwidth Memory (HBM) on Alveo FPGAs and Vitis HLS (BT)
Publications
2024
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ABACUS: ASIP-based Avro Schema-customizable Parser Acceleration on FPGAs
International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) (Kielce, 3. April 2024 - 5. April 2024)
In: IEEE Proceedings of the 27th International Symposium on Design and Diagnostics of Electronic Circuits & Systems 2024
DOI: 10.1109/DDECS60919.2024.10508904
BibTeX: Download - , , :
JSON-CooP: A JSON Decompression/Parsing Co-Design for FPGAs
International Conference on Field-Programmable Logic and Applications (FPL) (Turin, 2. September 2024 - 6. September 2024)
In: IEEE Proceedings of the 34th International Conference on Field-Programmable Logic and Applications 2024
DOI: 10.1109/FPL64840.2024.00012
BibTeX: Download
2023
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An FPGA Avro Parser Generator for Accelerated Data Stream Processing
2nd Workshop on Novel Data Management Ideas on Heterogeneous (Co-)Processors (NoDMC) (Dresden, 6. März 2023 - 10. März 2023)
In: Proceedings of the 2nd Workshop on Novel Data Management Ideas on Heterogeneous (Co-)Processors (NoDMC) 2023
DOI: 10.18420/BTW2023-46
BibTeX: Download - , , :
SPEAR-JSON: Selective parsing of JSON to enable accelerated stream processing on FPGAs
International Conference on Field-Programmable Logic and Applications (FPL) (Göteborg, 4. September 2023 - 8. September 2023)
In: IEEE Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications 2023
DOI: 10.1109/FPL60245.2023.00034
BibTeX: Download
2022
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Raw Filtering of JSON data on FPGAs
Design, Automation and Test in Europe Conference (DATE) (Antwerpen, 14. März 2022 - 23. März 2022)
In: Proceedings of the 2022 Conference & Exhibition on Design, Automation & Test in Europe 2022
DOI: 10.23919/DATE54114.2022.9774696
BibTeX: Download - , , :
Auto-Tuning of Raw Filters for FPGAs
International Conference on Field-Programmable Logic and Applications (FPL) (Belfast, United Kingdom, 29. August 2022 - 2. September 2022)
In: IEEE Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications 2022
DOI: 10.1109/FPL57034.2022.00036
BibTeX: Download